LTSpice
The predictive transistor model files developed in the PTM project. PTM evolved from the earlier Berkeley Predictive Technology Model by the Device Group, University of California, Berkerley. From 2005 to 2012, PTM developed models for bulk CMOS and FinFET devices
PTM for Bulk CMOS Models
The physical gate length is slightly smaller than the technological node
350nm : Model File Parameters: Vdd=3.3V, Wmin=0.6µm, Lmin=0.4µm
250nm : Model File Parameters: Vdd=2.5V, Wmin=0.36µm, Lmin=0.25µm
180nm : Model File Parameters: Vdd=1.8V, Wmin=0.27µm, Lmin=0.18µm
130nm : Model File Parameters: Vdd=1.2V/1.5V, Wmin=0.16µm, Lmin=0.13µm
90nm : Model File Parameters: Vdd=1.2V/1V, Wmin=0.18µm, Lmin=0.09µm
65nm : Model File Parameters: Vdd=1.2V/1V, Wmin=0.13µm, Lmin=0.065µm
For high-performance (HP) and low-power (LP) applications: